View L6482H_8385787.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. may 2014 docid023768 rev 4 1/73 l6482 cspin?: microstepping motor co ntroller with motion engine and spi datasheet ? production data features ? operating voltage: 7.5 v - 85 v ? dual full bridge gate driver for n-channel mosfets ? fully programmable gate driving ? embedded miller clamp function ? programmable speed profile ? up to 1/16 microstepping ? advanced current control with auto-adaptive decay mode ? integrated voltage regulators ? spi interface ? low quiescent standby currents ? programmable non dissipative overcurrent protection ? overtemperature protection applications ? bipolar stepper motor description the l6482 device, realized in analog mixed signal technology, is an advanced fully integrated solution suitable for dr iving two-phase bipolar stepper motors with microstepping. it integrates a dual full bridge gate driver for n-channel mosfet power stages with embedded non dissipative overcurrent protection. thanks to a new curr ent control, a 1/16 microstepping is achiev ed through an adaptive decay mode which outperforms traditional implementations. the digital control core can generate user defined motion profiles with acceleration, deceleration, speed or target position easily programmed through a dedicated register set. all application commands and data registers, including those used to set analog values (i.e. current protection trip point, deadtime, pwm frequency, etc.) are sent through a standard 5-mbit/s spi. a very rich set of protections (thermal, low bus voltage, overcurrent and motor stall) makes the l6482 device ?bullet proof?, as required by the most demanding motor control applications. htssop38 table 1. device summary order code package packaging L6482H htssop38 tube L6482Htr htssop38 tape and reel www.st.com
contents l6482 2/73 docid023768 rev 4 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 device power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 logic i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 automatic full-step and boost modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 absolute position counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 programmable speed profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 motor control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7.1 constant speed commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7.2 positioning commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7.3 motion commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.7.4 stop commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7.5 step-clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7.6 gountil and releasesw commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.8 internal oscillator and oscillator driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8.1 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.9 overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
docid023768 rev 4 3/73 l6482 contents 73 6.10 undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11 vs undervoltage lockout (uvlo_adc) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.12 thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.13 reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.14 external switch (sw pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.15 programmable gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.16 deadtime and blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.17 integrated analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.18 supply management and internal voltage regulators . . . . . . . . . . . . . . . . 33 6.19 busy/sync pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.20 flag pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 phase current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 auto-adjusted decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 auto-adjusted fast decay during the falling steps . . . . . . . . . . . . . . . . . . . 38 7.4 torque regulation (output current amplitude regulation) . . . . . . . . . . . . . . 39 8 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 register and flag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.1 abs_pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1.2 el_pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1.3 mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.4 speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.5 acc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.6 dec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.7 max_speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1.8 min_speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1.9 fs_spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1.10 tval_hold, tval_run, tval_acc and tval_dec . . . . . . . . . . . . 47 9.1.11 t_fast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1.12 ton_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1.13 toff_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.1.14 adc_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
contents l6482 4/73 docid023768 rev 4 9.1.15 ocd_th . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1.16 step_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1.17 alarm_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1.18 gatecfg1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1.19 gatecfg2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.20 config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.1.21 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2 application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.1 command management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2.2 nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.3 setparam (param, value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4 getparam (param) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.5 run (dir, spd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.2.6 stepclock (dir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.2.7 move (dir, n_step) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.8 goto (abs_pos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.9 goto_dir (dir, abs_pos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.2.10 gountil (act, dir, spd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.2.11 releasesw (act, dir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.12 gohome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.13 gomark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.14 resetpos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.15 resetdevice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.16 softstop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.17 hardstop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2.18 softhiz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2.19 hardhiz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2.20 getstatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
docid023768 rev 4 5/73 l6482 list of tables 73 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. typical application values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. cl values according to external oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. uvlo thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10. thermal protection summarizing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 11. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 12. el_pos register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 13. min_speed register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 14. fs_spd register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. torque regulation by tval_h old, tval_acc, tval_dec and tval_run registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 16. fs_spd register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 17. maximum fast decay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 18. minimum on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 19. minimum off-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 20. adc_out value and torque regulation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 21. overcurrent detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 22. step_mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 23. step mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 24. sync output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 25. sync signal source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. alarm_en register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. gatecfg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 28. igate parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 29. tcc parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 30. tboost parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 31. gatecfg2 register (voltage mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. tdt parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 33. tblank parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 34. config register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 35. oscillator management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 36. external switch hardstop interrup t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 37. overcurrent event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 38. programmable v cc regulator output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 39. programmable uvlo thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 table 40. external torque regulation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 41. switching period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 42. motor supply voltage compensation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 43. status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 44. status register th_status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 45. status register dir bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 46. status register mot_status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 47. application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
list of tables l6482 6/73 docid023768 rev 4 table 48. nop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 49. setparam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 50. getparam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 51. run command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 52. stepclock command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 53. move command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 54. goto command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 55. goto_dir command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 56. gountil command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 57. releasesw command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 table 58. gohome command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 59. gomark command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 60. resetpos command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 61. resetdevice command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 62. softstop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 63. hardstop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 64. softhiz command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 65. hardhiz command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 66. getstatus command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 67. htssop38 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 68. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
docid023768 rev 4 7/73 l6482 list of figures 73 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. charge pump circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5. normal mode and microstepping (16 microsteps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. automatic full-step switching in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. automatic full-step switching in boost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. speed profile in infinite acceleration/deceleratio n mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. constant speed command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. positioning command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. motion command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. oscin and oscout pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. overcurrent detection - principle scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 figure 14. external switch connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 15. gate driving currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 16. device supply pin management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17. predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18. non-predictive current control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 19. adaptive decay - fast decay tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 20. adaptive decay - switch from normal to slow + fast decay mode and vi ce versa . . . . . . . . 39 figure 21. fast decay tuning during the fa lling steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 22. current sensing and reference voltage generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 23. spi timings diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 24. daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 25. command with 3-byte argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 26. command with 3-byte response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 27. command response aborted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 28. htssop38 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 29. htssop38 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
block diagram l6482 8/73 docid023768 rev 4 1 block diagram figure 1. block diagram adc charge pump v dd spi current sensing stby/reset flag cs ck sdo sdi busy/sync sw stck dgnd vdd adcin vcc cp vboot pgnd vs core logic vcc hvga1 lvga1 hvga2 lvga2 hvb1 lvgb1 outa1 outa2 outb1 hvgb2 lvgb2 outb2 vboot vboot vboot vboot vsensea vsenseb agnd vcc vcc vcc voltage reg. vcc vsreg vcc reg ext. osc. driver & clock gen. oscin oscout 16 mhz oscillator temperature sensing vreg voltage reg. vreg am15031v1
docid023768 rev 4 9/73 l6482 electrical data 73 2 electrical data 2.1 absolute maximum ratings table 2. absolute maximum ratings symbol parameter test condition value unit v dd logic interface supply voltage 5.5 v v reg logic supply voltage 3.6 v s motor supply voltage 95 v v cc low-side gate driver supply voltage 18 v v boot boot voltage 100 v ? v boot high-side gate driver supply voltage (v boot - v s ) 0 to 20 v v sreg internal v cc regulator supply voltage 95 v v ccreg internal v reg regulator supply voltage 18 v v out1a v out2a v out1b v out2b full bridge output voltage dc -5 to v boot v ac -15 to v boot sr out full bridge output slew rate (10% - 90%) 10 v/ns v hvg1a v hvg2a v hvg1b v hvg2b high-side output driver voltage v out to v boot v ? v hvg1a ? v hvg2a ? v hvg1b ? v hvg2b high-side output driver to respective bridge output voltage(v hvg - v out ) 15 v v lvg1a v lvg2a v lvg1b v lvg2b low-side output driver voltage v cc + 0.3 v i gate-clamp high-side gate voltage clamp current capability 100 ma v adcin integrated adc input voltage r ange (adcin pin) -0.3 to 3.6 v v out_diff differential voltage between vboot, vs, out1a, out2a, pgnd and vboot, vs, out1b, out2b, pgnd pins 100 v v in logic inputs voltage range -0.3 to 5.5 v t s t op storage and operating junction temperature -40 to 150 c p tot total power dissipation (t amb = 25 oc) (1) 4w 1. htssop38 mounted on a four-layer fr4 pcb wi th a dissipating copper surface of about 30 cm 2 .
electrical data l6482 10/73 docid023768 rev 4 2.2 recommended operating conditions 2.3 thermal data table 3. recommended operating conditions symbol parameter test condition min. typ. max. unit v dd logic interface supply voltage 3.3 v logic outputs 3.3 v 5 v logic outputs 5 v reg logic supply voltage 3.3 v v s motor supply voltage v sreg 85 v v sreg internal v cc voltage regulator v cc voltage internally generated v cc +3 v s v v cc gate driver supply voltage v cc voltage imposed by external source (v sreg = v cc ) 7.5 15 v v ccreg internal v reg voltage regulator supply voltage v reg voltage internally generated 6.3 v cc v v adc integrated adc input voltage (adcin pin) 0v reg v table 4. thermal data symbol parameter package typ. unit r thj-a thermal resistance junction to ambient htssop38 (1) 31 c/w 1. htssop38 mounted on a four-layer fr4 pcb with a dissipating copper surface of about 30 cm 2 .
docid023768 rev 4 11/73 l6482 electrical characteristics 73 3 electrical characteristics v s = 48 v ; v cc = 7.5 v; t j = 25 c, unless otherwise specified. table 5. electrical characteristics symbol parameter test condition min. typ. max. unit general v ccthon v cc uvlo turn-on threshold uvlo_val set high (1) 9.9 10.4 10.9 v uvlo_val set low (1) 6.5 6.9 7.3 v v ccthoff v cc uvlo turn-off threshold uvlo_val set high (1) 9.5 10 10.5 v uvlo_val set low (1) 5.9 6.3 6.7 v ? v bootthon v boot - v s uvlo turn-on threshold uvlo_val set high (1) 8.6 9.2 9.8 v uvlo_val set low (1) 5.7 6 6.3 v ? v bootthoff v boot - v s uvlo turn-off threshold uvlo_val set high (1) 8.2 8.8 9.5 v uvlo_val set low (1) 5.3 5.5 5.8 v v regthon v reg turn-on threshold (1) 2.8 3 3.18 v v regthoff v reg turn-off threshold (1) 2.2 2.4 2.5 v i vregqu undervoltage v reg quiescent supply current v ccreg = v reg < 2.2 v 40 ? a i vregq quiescent v sreg supply current v ccreg = v reg = 3.3 v, internal oscillator selected (1) 3.8 ma i vsregq quiescent v sreg supply current v ccreg = v reg = 15 v 6.5 ma thermal protection t j(wrn)set thermal warning temperature 135 c t j(wrn)rec thermal warning reco very temperature 125 c t j(off)set thermal bridge shutdown temperature 155 c t j(off)rec thermal bridge sh utdown recovery temperature 145 c t j(sd)set thermal device shutdown temperature 170 c t j(sd)rec thermal device shutdown recovery temperature 130 c charge pump v pump voltage swing for charge pump oscillator v cc v f pump,min minimum charge pump oscillator frequency (2) 660 khz f pump,max maximum charge pump oscillator frequency (2) 800 khz
electrical characteristics l6482 12/73 docid023768 rev 4 r pumphs charge pump high-side r ds(on) resistance 10 ? r pumpls charge pump low-side r ds(on) resistance 10 ? i boot average boot current 2.6 ma gate driver outputs i gate,sink programmable high-side and low-side gate sink current v s = 38 v v hvgx - v outx > 3 v v lvgx > 3 v 2.4 4 5.6 ma 5.4 8 10.6 11.3 16 20.7 17.3 24 30.7 23.2 32 40.8 50.2 64 77.8 81 96 113 i gate,source programmable high-side and low-side gate source current v s = 38 v v bootx - v hvgx > 3.5 v v cc -v lvgx > 3.5 v 2.8 4 5.2 ma 5.8 8 10.2 12 16 20 18 24 30 24 32 40 51 64 77 82 96 112 i ob high-side and low-side turn-off overboost gate current 85 103 117 ma r clamp(ls) low-side gate driver miller clamp resistance 6.5 10 ? r clamp(hs) high-side gate driver miller clamp resistance 310 ? v gate-clamp high-side gate voltage clamp i gate-clamp = 100 ma 16.7 v t cc programmable constant gate current time (2) tcc = ?00000? 125 ns tcc = 11111 3750 t ob programmable. turn-off overboost; gate current time (2) tboost = ?001?, internal oscillator 62.5 ns tboost =?111? 1000 i dss leakage current out = v s 100 ? a out = gnd -100 ? a t r rise time i gate = 96 ma v cc = 15 v c gate = 15 nf 2.5 ? s table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
docid023768 rev 4 13/73 l6482 electrical characteristics 73 t f fall time i gate = 96 ma v cc = 15 v c gate = 15 nf 2.5 ? s srgate gate driver output slew rate i gate = 96 ma v cc = 15 v c gate = 15 nf 6v/ ? s deadtime and blanking t dt programmable deadtime (2) tdt = '00000' 125 ns tdt = ?11111? 4000 t blank programmable blanking time (2) tblank = '000' 125 ns tblank = ?111? 1000 logic v il low level logic input voltage 0.8 v v ih high level logic input voltage 2 v i ih high level logic input current v in = 5 v, vddio = 5 v 1 a i il low level logic input current v in = 0 v, vddio = 5 v -1 a v ol low level logic output voltage (3) v dd = 3.3 v, i ol = 4 ma 0.3 v v dd = 5 v, i ol = 4 ma 0.3 v oh high level logic output voltage v dd = 3.3 v, i oh = 4 ma 2.4 v v dd = 5 v, i oh = 4 ma 4.7 r pucs cs pull-up resistor 430 k ? r pdrst stby/reset pull-down resistor 450 r pusw sw pull-up resistor 80 t high,stck step-clock input high time 300 ns t low,stck step-clock input low time 300 ns internal oscillator and external oscillator driver f osc,int internal oscillator frequency t j = 25 c -5% 16 +5% mhz f osc,ext programmable external oscillator frequency 832mhz v oscouth oscout clock source high leve l voltage internal oscillator 2.4 v v oscoutl oscout clock source low level voltage internal oscillator 0.3 v t roscout t foscout oscout clock source rise and fa ll time internal oscillator 10 ns t high oscout clock source high time internal oscillator 31.25 ns table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
electrical characteristics l6482 14/73 docid023768 rev 4 t extosc internal to external oscillator switching delay 3ms t intosc external to internal oscillator switching delay 100 s spi f ck,max maximum spi clock frequency (4) 5mhz t rck t fck spi clock rise and fall time (4) 1s t hck t lck spi clock high and low time (4) 90 ns t setcs chip select setup time (4) 30 ns t holcs chip select hold time (4) 30 ns t discs deselect time (4) 625 ns t setsdi data input setup time (4) 20 ns t holsdi data input hold time (4) 30 ns t ensdo data output enable time (4) 95 ns t dissdo data output disable time (4) 95 ns t vsdo data output valid time (4) 35 ns t holsdo data output hold time (4) 0ns current control v ref, max maximum reference voltage 1000 mv v ref, min minimum reference voltage 7.8 mv overcurrent protection v ocd programmable overcurrent detection voltage v ds threshold ocd_th = ?11111? 800 1000 1100 mv ocd_th = ?00000? 27 31 35 mv ocd_th = ?01001? 270 312.5 344 mv ocd_th = ?10011? 500 625 688 mv t ocd,comp ocd comparator delay 100 200 ns t ocd,flag ocd to flag signal delay time 230 530 ns t ocd,sd ocd to shutdown delay time ocd_th = '11111' ocd event to 90% of gate voltage 400 630 ns table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
docid023768 rev 4 15/73 l6482 electrical characteristics 73 standby i stby standby mode supply current (vsreg pin) v cc = v ccreg = 7.5 v v sreg = 48 v 42 a v cc = v ccreg = 7.5 v v sreg = 18 v 37.5 i stby,vreg standby mode supply current (vreg pin) 6 a t stby,min minimum standby time 0.5 ms t logicwu logic power-on and wake-up time 500 s t cpwu charge pump power-on and wake-up time power bridges disabled, c p = 10 nf, c boot = 220 nf, v cc = 15 v 1ms internal voltage regulators v ccout internal v cc voltage regulator output voltage low (default), i cc = 10 ma 7.3 7.5 v high, i cc = 10 ma 4 15 v ccreg, drop v sreg to v cc dropout voltage i cc = 50 ma 3 v p cc internal v cc voltage regulator power dissipation 2.5 w v regout internal v reg voltage regulator output voltage i reg = 10 ma 3.13 5 3.3 v v sreg, drop v ccreg to v reg dropout voltage i reg = 50 ma 3 v i regout internal v reg voltage regulator output current vreg pin shorted to ground 125 ma i regout,stb y internal v reg voltage regulator output standby current vreg pin shorted to ground 55 ma p reg internal v reg voltage regulator power dissipation 0.5 w integrated analog-to-digital converter n adc analog-to-digital converter resolution 5 bit v adc,ref analog-to-digital converter reference voltage 3.3 v f s analog-to-digital converter sampling frequency (2) f osc/512 khz v adc,uvlo adcin uvlo threshold 1.05 1.16 1.35 v 1. guaranteed in the temperature range -25 to 125 c . 2. the value accuracy is dependent on oscillator frequency accuracy ( section 6.8 on page 26 ). 3. flag and busy open drain outputs included. 4. see figure 22 on page 41 . table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
pin connection l6482 16/73 docid023768 rev 4 4 pin connection pin list figure 2. pin connection (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 vccreg vcc cp vboot pgnd adcin nc hvga1 lvga1 outa1 hvgb1 outb1 lvgb1 vs vsreg vreg oscin oscout agnd vddio sw stck dgnd sdo sdi ck epad hvga2 sensea senseb lvga2 outa2 hvgb2 outb2 lvgb2 cs flag stby/reset busy/sync am15032v1 table 6. pin description no. name type function 11 vccreg power supply internal v reg voltage regulator supply voltage 13 vreg power supply logic supply voltage 27 vdd power supply logic interface supply voltage 12 vsreg power supply internal v cc voltage regulator supply voltage 10 vcc power supply gate driver supply voltage 14 oscin analog input oscillator pin1. to connec t an external oscillat or or clock source. 15 oscout analog output oscillator pin2. to connect an external oscillator. when the internal oscillator is used, this pin can supply a 2/4/8/16 mhz clock. 9 cp output charge pump oscillator output 7 vboot power supply bootstrap voltage needed for driving the high-side power dmos of both bridges (a and b). 5 adcin analog input internal analog-to-digital converter input 6 vs power supply motor voltage
docid023768 rev 4 17/73 l6482 pin connection 73 3 hvga1 power output high-side half-bridge a1 gate driver output 36 hvga2 power output high-side half -bridge a2 gate driver output 17 hvgb1 power output high-side half -bridge b1 gate driver output 22 hvgb2 power output high-side half -bridge b2 gate driver output 1 lvga1 power output low-side half-bridge a1 gate driver output 38 lvga2 power output low-side half-bridge a2 gate driver output 19 lvgb1 power output low-side half-bridge b1 gate driver output 20 lvgb2 power output low-side half-bridge b2 gate driver output 8 pgnd ground power ground pins. they must be connected to other ground pins 35 sensea analog input phase a current sensing input 23 senseb analog input phase b current sensing input 2 outa1 power input full bridge a output 1 37 outa2 power input full bridge a output 2 18 outb1 power input full bridge b output 1 21 outb2 power input full bridge b output 2 16 agnd ground analog ground. it must be connected to other ground pins 33 sw logical input external switch input pin 29 dgnd ground digital ground. it must be connected to other ground pins 28 sdo logical output data output pin for serial interface 26 sdi logical input data input pin for serial interface 25 ck logical input serial interface clock 24 cs logical input chip select input pin for serial interface 30 busy /sync open drain output by default, the busy / sync pin is forced low when the device is performing a command. the pin can be programmed in order to generate a synchronization signal. 31 flag open drain output status flag pin. an internal open drain transistor can pull the pin to gnd when a programmed alarm cond ition occurs (step loss, ocd, thermal pre-warning or shutdown, uvlo, wrong command, non- performable command). 34 stby reset logical input standby and reset pin. low logic level puts the device in standby mode and reset logic. if not used, it should be connected to v reg . 32 stck logical input step-clock input epad exposed pad ground exposed pad. it mu st be connected to other ground pins. table 6. pin description (continued) no. name type function
typical applications l6482 18/73 docid023768 rev 4 5 typical applications figure 3. typical application schematic table 7. typical application values name value c vspol 220 f c vs 220 nf c boot 470 nf c fly 47 nf c vsreg 100 nf c vcc 470 nf c vccreg 100 nf c vreg 100 nf c vregpol 22 f c vdd 100 nf d1 charge pump diodes q1, q2, q3, q4, q5, q6, q7, q8 std25n10f7 r pu 39 k ? r sense 0.2 ? (maximum phase current 5 a) ck sdo sdi sw stck dgnd vdd adcin analog signal vcc cp vboot pgnd vs stby/reset flag cs busy/sync hvga1 l vga1 lvga2 hvga2 hv gb1 lvgb1 outa1 outa2 outb1 lvgb2 hvgb2 senseb outb2 sensea agnd vsreg vccreg oscin oscout vreg l6482 c fly c v s c vcc c vccreg c vdd c vsreg c boo t c vspol v s c vreg c vregpol (10.5v - 85v ) d1 q1 q2 q4 q3 r sense r sense q5 q6 q8 q7 motor r pu r pu host am15033v1
docid023768 rev 4 19/73 l6482 functional description 73 6 functional description 6.1 device power-up during power-up, the device is under reset (a ll logic ios disabled and power bridges in high impedance state) until the following conditions are satisfied: ? v reg is greater than v regthon ? internal oscillator is operative ? stby /reset input is forced high. after power-up, the device state is the following: ? parameters are set to default ? internal logic is driven by internal oscillator and a 2- mhz clock is provided by the oscout pin ? bridges are disabled (high impedance). ? flag output is forced lo w (uvlo failure indication). after power-up, a period of t logicwu must pass before applying a command to allow proper oscillator and logic startup. any movement command makes the device exit from high z state (hardstop and softstop included). 6.2 logic i/o pins cs , ck, sdi, stck, sw and stby /reset are ttl/cmos 3.3 v -5 v compatible logic inputs. pin sdo is a ttl/cmos compatible logic output . vdd pin voltage imposes a logical output voltage range. pins flag and busy /sync are open drain outputs. sw and cs inputs are internally pulled up to v dd and stby /reset input is internally pulled down to ground. 6.3 charge pump to ensure the correct driving of the high-side gate drivers, a voltage higher than the motor power supply voltage needs to be applied to the vboot pin. the high-side gate driver supply voltage v boot is obtained through an oscillato r and a few external components realizing a charge pump (see figure 4 ).
functional description l6482 20/73 docid023768 rev 4 figure 4. charge pump circuitry 6.4 microstepping the driver is able to divide the single step in to up to 16 microsteps. stepping mode can be programmed by the step_sel paramete r in the step_mode register ( table 22 on page 50 ). step mode can only be changed when bridges are disabled. every time the step mode is changed, the electrical position (i.e. the point of microstepping sine wave that is generated) is reset to zero and the absolute position counter value ( section 6.5 ) becomes meaningless. figure 5. normal mode and microstepping (16 microsteps) v s v s + v cp d1 d2 v cp f pump to high-side gate drivers v s + v cp v d1 c boot c fly d1 d2 vboot cp v dd v v charge pump oscillator am15034v1 step 1 step 1 step 2 step 3 step 4 step 1 reset position step 1 step 2 step 3 step 4 normal driving microstepping phase a current phase b current phase a current phase b current microsteps 16 16 microsteps 16 16 reset position microsteps microsteps microsteps am15035v1
docid023768 rev 4 21/73 l6482 functional description 73 automatic full-step and boost modes when motor speed is greater than a programmable full-step speed threshold, the l6482 device switches automatically to full-step mode; the driving mode returns to microstepping when motor speed decreases below the full-step speed threshold. the switching between the microstepping and full-step mode and vice versa is always performed at an electrical position multiple of ? /4 ( figure 6 and figure 7 ). full-step speed threshold is set through the related parameter in the fs_spd register ( section 9.1.9 on page 47 ). when the boost_mode bit of the fs_spd regist er is low (default), the amplitude of the voltage squarewave in full-step mode is equal to the peak of the voltage sine wave multiplied by sine( ? /4) ( figure 6 ). this avoids the current drop between the two driving modes. when the boost_mode bit of the fs_spd regi ster is high, the amplitude of the voltage squarewave in full-step mode is equal to the peak of the voltage sine wave ( figure 7 ). that improves the output current increasing the maximum motor torque. figure 6. automatic full-step switching in normal mode phase a phase b (2n+1) x /4 (2n+1) x /4 full-step microstepping microstepping v peak sin( /4 )x v peak am15036v1
functional description l6482 22/73 docid023768 rev 4 figure 7. automatic full-step switching in boost mode 6.5 absolute position counter an internal 22-bit register (abs_pos) records all the motor motions according to the selected step mode; the stored value unit is e qual to the selected step mode (full, half, quarter, etc.). the position range is from -2 21 to +2 21 -1 steps (see section 9.1.1 on page 44 ). 6.6 programmable speed profiles the user can easily program a customiz ed speed profile defining independently acceleration, deceleration, and maximum a nd minimum speed values by acc, dec, max_speed and min_speed regi sters respectively (see section 9.1.5 on page 45 , 9.1.6 on page 45 , 9.1.7 on page 46 and 9.1.8 on page 46 ). when a command is sent to the device, th e integrated logic generates the microstep frequency profile that performs a motor motion compliant to speed profile boundaries. all acceleration parameters are expressed in step/tick 2 and all speed parameters are expressed in step/tick; the unit of measur ement does not depend on the selected step mode. acceleration and deceleration parameters range from 2 -40 to (2 12 -2) ?? 2 -40 step/tick 2 (equivalent to 14.55 to 59590 step/s 2 ). minimum speed parameter ranges from 0 to (2 12 - 1 ) ?? 2 -24 step/tick (equivalent to 0 to 976.3 step/s). maximum speed parameter ranges from 2 -18 to (2 10 -1) ?? 2 -18 step/tick (equivalent to 15.25 to 15610 step/s). phase a phase b (2n+1) x /4 (2n+1) x /4 full-step microstepping microstepping v peak v peak am15037v1
docid023768 rev 4 23/73 l6482 functional description 73 6.7 motor control commands the l6482 can accept different types of commands: ? constant speed commands (run, gountil, releasesw) ? absolute positioning commands (goto, goto_dir, gohome, gomark) ? motion commands (move) ? stop commands (softstop, hardstop, softhiz, hardhiz). for detailed command descriptions refer to section 9.2 on page 60 . 6.7.1 constant speed commands a constant speed command produces a motion in order to reach and maintain a user- defined target speed starting from the prog rammed minimum speed (s et in the min_speed register) and with the programmed acceleration/de celeration value (set in the acc and dec registers). a new constant speed command can be requested anytime. figure 8. constant speed command examples 6.7.2 positioning commands an absolute positioning command produces a motion in order to reach a user-defined position that is sent to the device together with the command. the position can be reached performing the minimum path (minimum physic al distance) or forcing a direction (see figure 9 ). performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed). note that with some speed profiles or positioning commands, the deceleration phase can start before the maximum speed is reached. am15039v1 spd1 spd2 spd3 spd4 run(spd2,fw) time speed (step frequency) run(spd3,fw) run(spd1,fw) run(spd4,bw) minimum speed minimum speed
functional description l6482 24/73 docid023768 rev 4 figure 9. positioning command examples 6.7.3 motion commands motion commands produce a motion in order to perform a user-defined number of microsteps in a user-defined direction that ar e sent to the device together with the command (see figure 10 ). performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed). note that with some speed profiles or motion commands, the deceleration phase can start before the maximum speed is reached. figure 10. motion command examples am15040v1 forward direction 0 -2 21 +2 21 -1 0 -2 21 +2 21 -1 present position target position present position target position goto(target pos) goto_dir(target pos,fw) programmed acceleration speed programmed maximum speed programmed minimum speed time programmed deceleration programmed number of microsteps programmed acceleration speed programmed maximum speed programmed minimum speed time programmed deceleration programmed number of microsteps note: with some acceleration/decelaration profiles the programmed maximum speed is never reached am15041v1
docid023768 rev 4 25/73 l6482 functional description 73 6.7.4 stop commands a stop command forces the motor to stop. stop commands can be sent anytime. the softstop command causes the motor to decelerate with a programmed deceleration value until the min_speed value is reached and then stops the motor keeping the rotor position (a holding torque is applied). the hardstop command stops the motor instantly, ignoring deceleration constraints and keeping the rotor position (a holding torque is applied). the softhiz command causes the motor to decelerate with a programmed deceleration value until the min_speed valu e is reached and then forces the bridges into high impedance state (no holding torque is present). the hardhiz command instantly forces the bridges into high impedance state (no holding torque is present). 6.7.5 step-clock mode in step-clock mode the motor motion is defined by the step-clock signal applied to the stck pin. at each step-clock rising edge, the motor is moved one microstep in the programmed direction and the absolute position is consequently updated. when the system is in step-c lock mode, the sck_mod flag in the status register is raised, the speed register is set to zero an d the motor status is considered stopped regardless of the stck signal frequency (the mot_status parameter in the status register equal to ?00?). 6.7.6 gountil and releasesw commands in most applications the powe r-up position of the stepper motor is undefined, so an initialization algorithm driving the motor to a known position is necessary. the gountil and releasesw commands can be us ed in combination with external switch input (see section 6.14 on page 30 ) to easily initialize the motor position. the gountil command makes the motor run at ta rget constant speed until the sw input is forced low (falling edge). when this event oc curs, one of the following actions can be performed: ? abs_pos register is set to ze ro (home position) and the motor decelerates to zero speed (as a softstop command) ? abs_pos register value is stor ed in the mark register an d the motor decelerates to zero speed (as a softstop command). if the sw_mode bit of the config register is se t to ?0?, the motor do es not decelerate but it immediately stops (as a hardstop command). the releasesw command makes the motor run at a programmed minimum speed until the sw input is forced high (rising edge). when this event occurs, one of the following actions can be performed: ? abs_pos register is set to zero (home position) and th e motor immediately stops (as a hardstop command) ? abs_pos register value is st ored in the mark register and the motor immediately stops (as a hardstop command). if the programmed minimum speed is less than 5 step/s, the motor is driven at 5 step/s.
functional description l6482 26/73 docid023768 rev 4 6.8 internal oscillator and oscillator driver the control logic clock can be supplied by t he internal 16-mhz osc illator, an external oscillator (crystal or ceramic reso nator) or a direct clock signal. these working modes can be selected by ext_clk and osc_sel parameters in the config register (see table 35 on page 56 ). at power-up the device st arts using the internal oscillator and provides a 2-mhz clock signal on the oscout pin. attention: in any case, before changing clock source configuration, a hardware reset is mandatory. switching to different clock configurations during operation may cause unexpected behavior. 6.8.1 internal oscillator in this mode the internal oscillator is activa ted and oscin is unused. if the oscout clock source is enabled, the oscout pin provides a 2, 4, 8 or 16-mhz clock signal (according to osc_sel value); otherwise it is unused (see figure 11 ). 6.8.2 external clock source two types of external clock source can be sele cted: crystal/ceramic resonator or direct clock source. four programmable clock frequencies ar e available for each external clock source: 8, 16, 24 and 32-mhz. when an external crystal/resonator is select ed, the oscin and oscout pins are used to drive the crystal/resonator (see figure 11 ). the crystal/resonator and load capacitors (c l ) must be placed as close as possible to the pins. refer to table 8 for the choice of the load capacitor value accord ing to the external oscillator frequency. if a direct clock source is used, it must be connected to the oscin pin and the oscout pin supplies the inverted oscin signal (see figure 11 ). the l6482 integrates a clock detection system that resets the device in the case of a failure of the external clock source (d irect or crystal/resonator). the monitoring of the clock source is disabled by default, it can be enabled setting high the wd_en bit in the gatecfg1 table 8. cl values according to external oscillator frequency crystal/resonator frequency (1) 1. first harmonic resonance frequency. c l (2) 2. lower esr value allows greater load capacitors to be driven. 8 mhz 25 pf (esr max = 80 ? ) 16 mhz 18 pf (esr max = 50 ? ) 24 mhz 15 pf (esr max = 40 ? ) 32 mhz 10 pf (esr max = 40 ? )
docid023768 rev 4 27/73 l6482 functional description 73 register ( section 9.1.18 on page 52 ). when the external clock s ource is selected, the device continues to work with the integrated os cillator for t extosc milliseconds and then the clock management system switches to the oscin input. figure 11. oscin and oscout pin configuration note: when oscin is unused, it should be left floating. when oscout is unused, it should be left floating. 6.9 overcurrent detection the l6482 measures the load curren t of each half-bridge sensing the v ds voltage of all the power mosfets ( figure 12 ). when any of the v ds voltages rise above the programmed threshold, the ocd flag in the status regist er is forced low until the event expires and a getstatus command is sent to the device ( section 9.1.21 on page 58 and section 9.2.20 on page 69 ). the overcurrent event expires when all the power mosfet v ds voltages fall below the programmed threshold. the overcurrent threshold can be programmed by the ocd_th register in one of 32 available values ranging from 31.25 mv to 1 v with steps of 31.25 mv ( table 21 on page 50 and section 9.1.17 on page 52 ). unused oscin oscout oscin oscout oscin oscout 2/4/8/16 mhz 8/16/24/32 mhz 8/16/24/32 mhz external oscillator configuration external clock source configuration internal oscillator configuration with clock generation oscin oscout internal oscillator configuration without clock source unused unused osc_sel = "1xx" osc_sel = "0xx" c l c l ext_clk = "0" ext_clk = "1" am15042v1
functional description l6482 28/73 docid023768 rev 4 figure 12. overcurrent detection - principle scheme the overcurrent detection comparators are disabled, in order to avoid wrong voltage measurements, in the following cases: ? the respective half-bridge is in high impedance state (both mosfets forced off) ? the respective half-bridge is commutating ? the respective half-bridge is commutated and the programmed blanking time has not yet elapsed ? the respective gate is turned off. it is possible to set, if an overcurrent event causes the bridge turn-off or not, through the oc_sd bit in the config register. when the power bridges are turned off by an overcurrent event, they cannot be turned on until the ocd flag is released by a getstatus command. 6.10 undervoltage lockout (uvlo) the l6482 provides a programmable gate driver supply voltage uvlo protection. when one of the supply voltages of the gate driver (v cc for the low sides and v boot - v s for the high sides) falls below the respective turn-off threshold, an undervoltage event occurs. in this case, all mosfets are immediately turned off and the uvlo flag in the status register is forced low. the uvlo flag is forced low and the mosfets are kept off until the gate driver supply voltages return to above the respective turn-on threshold; in this case the undervoltage event expires and the uvlo flag can be released through a getstatus command. the uvlo thresholds can be selected between two sets according to the uvloval bit value in the config register. hvgxx outxx lvgxx vs gndx + - + - blanking ocd_hsxx ocd_lsxx current dac oc threshold gnd vs gnd logic core voltage comparator voltage comparator am15043v1
docid023768 rev 4 29/73 l6482 functional description 73 6.11 vs undervoltage lockout (uvlo_adc) the device provides an undervoltage signal of the integrated adc input voltage (the uvlo_adc flag in the status register). when v adcin falls below the v adc,uvlo value, the uvlo_adc flag is forced low a nd it is kept in this state un til the adcin voltage is greater than v adc,uvlo and a getstatus command is sent to the device. the adcin undervoltage event does not turn off the mosfets of the power bridges. the motor supply voltage undervoltage detection can be performed by means of this feature, connecting the adcin pin to vs through a voltage divider. 6.12 thermal warning and thermal shutdown an integrated sensor allows detection of th e internal temperature and implementation of a 3-level protection. when the t j(wrn)set threshold is reached, a warning signal is generated. this is the thermal warning condition and it expires when the temperature falls below the t j(wrn)rel threshold. when the t j(off)set threshold is reached, all the mosfets are turned off and the gate driving circuitry is disabled (miller clamps are still operative). this c ondition expires when the temperature falls below the t j(off)rel threshold. when the t j(sd)off threshold is reached, all the mosfets are tu rned off using miller clamps, the internal v cc voltage regulator is disabled and the current capability of the internal v reg voltage regulator is reduc ed (thermal shutdown). in th is condition, logic is still active (if supplied). the thermal shutdown co ndition only expires when the temperature goes below t j(sd)on . the thermal condition of the device is shown by th_status bits in the status register ( table 10 ). table 9. uvlo thresholds parameter uvloval 01 low-side gate driver supply turn-off threshold (v ccthoff ) 6.3 v 10 v low-side gate driver supply turn-on threshold (v ccthon ) 6.9 v 10.4 v high-side gate driver supply turn-off threshold ( ? v bootthoff ) 5.5 v 8.8 v high-side gate driver supply turn-on threshold ( ? v bootthoff ) 6 v 9.2 v
functional description l6482 30/73 docid023768 rev 4 6.13 reset and standby the device can be reset and put into standby mode through the stby /reset pin. when it is forced low, all the mosfets are turned off (high z state), the charge pump is stopped, the spi interface and control logic are disabled and the internal v reg voltage regulator maximum output current is limited; as a result , the l6482 device heavily reduces the power consumption. at the same time the register values are reset to their default and all the protection functions are disabled. the stby /reset input must be forc ed low at least for t stby,min in order to ensure the comple te switch to standby mode. on exiting standby mode, as we ll as for ic power-up, a delay must be given before applying a new command to allow proper oscillator and charge pump startu p. actual delay could vary according to the values of the charge pump external components. on exiting standby mode all the mosfets are off and the hiz flag is high. the registers can be reset to the default val ues without putting the device into standby mode through the resetdevice command ( section 9.2.15 on page 67 ). 6.14 external switch (sw pin) the sw input is inte rnally pulled up to v dd and detects if the pin is open or connected to ground (see figure 13 ). the sw_f bit of the status register indicates if the switch is open (?0?) or closed (?1?) ( section 9.1.21 on page 58 ); the bit value is refreshed at every system clock cycle (125 ns). the sw_evn flag of the status register is raised when a switch turn-on event (sw input falling edge) is detected ( section 9.1.21 ). a getstatus command rele ases the sw_evn flag ( section 9.2.20 on page 69 ). by default, a switch turn-on event causes a hardstop interrupt (sw_mode bit of the config register set to ?0?). otherwise (sw_mode bit of the config register set to ?1?), switch input events do not cause interrupts and the switch status information is at the user?s disposal ( table 36 on page 56 and section 9.1.20 on page 55 ). table 10. thermal protection summarizing table state set condition release condition description th_status normal normal operation state 00 warning t j > tj(wrn)set t j > tj(wrn)rel temperature warning: operation is not limited 01 bridge shutdown t j > tj(off)set t j > tj(off)rel high temperature protection: the mosfets are turned off and the gate drivers are disabled 10 device shutdown t j > tj(sd)set t j > tj(sd)rel overtemperature protection: the mosfets are turned off, the gate drivers are disabled, the internal v cc voltage regulator is disabled, the current capability of the internal v reg voltage regulator is limited, and the charge pump is disabled 11
docid023768 rev 4 31/73 l6482 functional description 73 the switch input can be used by gount il and releasesw commands as described in section 9.2.10 on page 65 and section 9.2.11 on page 66 . if the sw input is not used, it should be connected to v dd . 6.15 programmable gate drivers the l6482 integrates eight programmable gate dr ivers that allow the fitting of a wide range of applications. the following parameters can be adjusted: ? gate sink/source current (i gate ) ? controlled current time (t cc ) ? turn-off overboost time (t ob ). during turn-on, the gate driver charges the gate forcing an i gate current for all the controlled current time period. at the end of the contro lled current phase the gate of the external mosfet should be completely charged, otherw ise the gate driving circuitry continues to charge it using a holding current. this current is equal to i gate for the low-side gate drivers and 1 ma for the high-side ones. during turn-off, the gate driver discharges the gate sinking an i gate current for all the controlled current time period. at the beginn ing of turn-off an overboost phase can be added: in this case the gate driver sinks an i ob current for the programmed t ob period in order to rapidly reach the plateau region. at the end of the controlled current time the gate of the external mosfet should be completely charged, otherwise the gate driving circuitry discharges it using the integrated miller clamp. figure 13. external switch connection am15044v1 external switch sw v dd
functional description l6482 32/73 docid023768 rev 4 the gate current can be set to one of the following values: 4, 8, 16, 24, 32, 64 and 96 ma through the igate parameter in the gatecfg1 register (see section 9.1.18 on page 52 ). controlled current time can be programmed within range from 125 ns to 3.75 ? s with a resolution of 125 ns (tcc parameter in the gatecfg1 register) (see section 9.1.18 ). turn-off overboost time can be set to one of the following values: 0, 62.5, 125, 250 ns (tboost parameter in the gatecfg1 register). the 62.5 ns value is only available when clock frequency is 16 mhz or 32 mhz; when cl ock frequency is 8 mhz it is changed to 125 ns and when a 24-mhz clock is used it is changed to 83.3 ns. (see section 9.1.18 ). 6.16 deadtime and blanking time during the bridge commutation, a deadtime is added in order to avoid cross conductions. the deadtime can be programmed within a range from 125 ns to 4 ? s with a resolution of 125 ns (tdt parameter in the gatecfg2 register) (see section 9.1.19 on page 54 ). at the end of each commutation the overcurrent and stall detection comparators are disabled (blanking) in order to avoid the respective systems detecting body diode turn-off current peaks. the duration of blanking time is progra mmable through the tblank parameter in the gatecfg2 register at one of the following values: 125, 250, 375, 500, 625, 750, 875, 1000 ns (see section 9.1.19 ). 6.17 integrated analog -to-digital converter the l6482 integrates an n adc bit ramp-compare analog-to-digital converter with a reference voltage equal to v reg . the analog-to-digital converter input is available through the adcin pin and the conversion result is available in the adc_out register ( section 9.1.14 on page 50 ). the adc_out value can be used for torque regulation or can be at the user?s disposal. figure 14. gate driving currents gate current gate turn-on i gate i gate i ob t cc t ob t cc gate charged gate discharged gate turn-off am15045v1
docid023768 rev 4 33/73 l6482 functional description 73 6.18 supply management and internal voltage regulators the l6482 integrates two linear voltage regulators: the first one can be used to obtain gate driver supply starting from a higher voltage (e.g. the motor supply one). its output voltage can be set to 7.5 v or 15 v according to the vccval bit value (config register). the second linear voltage regulator can be used to obtain the 3.3 v logic supply voltage. the regulators are designed to supply the internal circuitry of the ic and should not be used to supply external components. the input and output voltages of both regulat ors are connected to external pins and the regulators are totally independent: in this way a very flexible supply management can be performed using external components or external supply voltages ( figure 15 ). figure 15. device supply pin management if v cc is externally supplied, the vsreg and vcc pins must be shorted (v sreg must be compliant with v cc range). if v reg is externally supplied, th e vccreg and vreg pins must be shorted and equal to 3.3 v. v sreg must be always less than v boot in order to avoid related esd protection diode turn- on. the device can be protected from this event by adding an external low drop diode between the vsreg and vs pins, charge pump diodes should be low drop too. v ccreg must be always less than v cc in order to avoid esd protection diode turn-on. the device can be protected from this event by a dding an external low drop diode between the vccreg and vsreg pins. both regulators provide a short-circuit pr otection limiting the load current within the respective maximum ratings. vboot cp vs vs r e g vcc vccreg vreg 7v5 - 15v 3v3 vboot cp vs vs r e g vcc vccreg vreg 7v5 - 15v 3v3 vbus using external components (zener diodes, resistors, ...) it is possible to reduce internal power dissipation constrains. vbus vcc 3.3 v all voltages are internally generated all voltages are externally supplied am15046v1
functional description l6482 34/73 docid023768 rev 4 6.19 busy/sync pin this pin is an open drain output which can be used as busy flag or synchronization signal according to the sync_en bit value (step_mode register) (see section 9.1.17 on page 52 ). 6.20 flag pin by default, an internal open drain transistor pulls the flag pin to ground when at least one of the following conditions occurs: ? power-up or standby/reset exit ? overcurrent detection ? thermal warning ? thermal shutdown ? uvlo ? uvlo on adc input ? switch turn-on event ? command error. it is possible to mask one or more alarm conditions by programming the alarm_en register (see section 9.1.17 and table 26 on page 52 ). if the corresponding bit of the alarm_en register is low, the alarm condition is masked and it does not cause a flag pin transition; all other actions im posed by alarm conditions are performed anyway. in case of daisy chain configuration, flag pins of different ics can be or-wired to save host controller gpios.
docid023768 rev 4 35/73 l6482 phase current control 73 7 phase current control the l6482 performs a new current control technique, named predictive current control, allowing the device to obtain the target averag e phase current. this method is described in detail in section 7.1 . furthermore, the l6482 automatically selects the better decay mode in order to follow the current profile. current control algorithm parameters can be programmed by t_fast, ton_min, toff_min and config registers (see section 9.1.11 on page 48 , 9.1.12 on page 48 , 9.1.13 on page 49 and 9.1.20 on page 55 for details). different current amplitude can be set for acceleration, deceleration and constant speed phases and when the motor is stopped th rough tval_acc, tval_dec, tval_run and tval_hold registers (see section 9.1.10 on page 47 ). the output current amplitude can also be regulated by the adcin voltage value (see section 7.4 on page 39 ). each bridge is driven by an independent control system that shares with the other bridge the control parameters only. 7.1 predictive current control unlike classical peak current control systems, that make the phase current decay when the target value is reached, this new method keeps the power bridge on for an extra time after reaching the current threshold. at each cycle the system measures the time required to reach the target current (t sense ). after that the power stage is kept in a ?predictive? on state (t pred ) for a time equal to the mean value of t sense in the last two control cycles (actual one and previous one), as shown in figure 16. figure 16. predictive current control at the end of the predictive on state the power stage is set in off state for a fixed time, as in a constant t off current control. during the off state both slow and fast decay can be predictive on state off state t sense (n-1) t off t off t pred (n) = t sense (n-1) + t sense (n) 2 i ref i out t pred (n-1) t sense (n) t pred (n) am15048v1
phase current control l6482 36/73 docid023768 rev 4 performed; the better decay combination is aut omatically selected by the l6482 device, as described in section 7.2 . as shown in figure 16 , the system is able to center the triangular wave on the desired reference value, improving dramatically the accu racy of the current control system: in fact the average value of a triangular wave is exactly equal to the middle point of each of its segment and at steady-state the predictive curr ent control tends to equalize the duration of the t sense and the t pred time. furthermore, the t off value is recalculated each time a new current value is requested (microstep change) in order to keep the pwm frequency as near as possible to the programmed one (tsw parameter in the config register). the device can be forced to work using cl assic peak current control setting low the pred_en bit in the config register (default condition). in this case, after the sense phase (t sense ) the power stage is set in off state, as shown in figure 17 . figure 17. non-predictive current control 7.2 auto-adjusted decay mode during the current control, the device automat ically selects the better decay mode in order to follow the curren t profile reducing the current ripple. at reset, the off-time is performed turning on both the low-side mos of the power stage and the current recirculates in the lowe r half of the bridge (slow decay). if, during a pwm cycle, the target current thre shold is reached in a time shorter than the ton_min value, a fast decay of toff_fast/8 (t_fast register) is immediately performed turning on the opposite mos of both half-bridges and the current recirculates back to the supply bus. after this time, the bridge returns to on state: if the time needed to reach the target current value is still less than ton_min, a new fast decay is performed with a period twice the previous one. otherwise, the normal contro l sequence is followe d as described in section 7.1 . the maximum fast decay duration is set by the toff_fast value. sense on state off state t off t off i ref i out am15049v1
docid023768 rev 4 37/73 l6482 phase current control 73 figure 18. adaptive decay - fast decay tuning when two or more fast decays are performed with the present target current, the control system adds a fast decay at the end of every off-time keeping the off state duration constant (t off is split into t off , slow and t off , fast ). when the current threshold is increased by a microstep change (rising step), the syst em returns to normal decay mode (slow decay only) and the t fast value is halved. stopping the motor or reaching the current si ne wave zero crossing causes the current control system to retu rn to the reset state. uhihuhqfhfxuuhqw vw idvwghfd\ w )$67 72))b)$67 qg idvwghfd\ w )$67 72))b)$67 1rwh vwdu wlqjiurp qg idvwghfd\wkhv\vwhpfrpelqhv idvwdqgvorzghfd\gxulqjwkh2))skdvh ug idvwghfd\ w )$67 72))b)$67 7rq!721b0,1 w )$67 72))b)$67 $0y
phase current control l6482 38/73 docid023768 rev 4 7.3 auto-adjusted fast deca y during the falling steps when the target current is dec reased by a microstep change (falling step), the device performs a fast decay in order to reach the new value as fast as possible. however, exceeding the fast duration could cause a strong ripple on the step change. the l6482 device automatically adjusts these fast decays reducing the current ripple. at reset the fast decay value (t fall ) is set to fall_step/4 (t_fast register). the t fall value is doubled every time, within the same fallin g step, an extra fast decay is necessary to obtain an on-time greater than ton_min (see section 9.1.12 on page 48 ). the maximum t fall value is equal to fall_step. at the next falling step, the system uses the last t fall value of the previous falling step. stopping the motor or reaching the current si ne wave zero crossing causes the current control system to retu rn to the reset state. figure 19. adaptive decay - switch from normal to slow + fast decay mode and vice versa time time reference current 1 st fast decay target current is increased (raising step) 2 nd fast decay system returns to slow decay mode and t fast vaule is halved switch to fast + slow decay mode t fast t off,fast t off,slow t off t off reference current am15051v1
docid023768 rev 4 39/73 l6482 phase current control 73 figure 20. fast decay tuning during the falling steps 7.4 torque regulation (output current amplitude regulation) the phase currents are monitored through two shunt resistors (one for each power bridge) connected to the respective sense pin (see figure 21 ). the integrated comparator compares the sense resistor voltage with the internal reference generated using the peak value, which is proportional to the output cu rrent amplitude, and the microstepping code. the comparison result is provided to the logi c in order to implement the current control algorithm as described in previous sections. the peak reference voltage can be regulated in two ways: writing tval_acc, tval_dec, tval_run and tval_hold r egisters or varying the adcin voltage value. the en_tqreg bit (config register) sets the torq ue regulation method. if this bit is high, adc_out prevalue is used to regulate output current amplitude (see table 20 on page 50 and section 9.1.14 on page 50 ). otherwise the internal analog-t o-digital converter is at the user?s disposal and the out put current amplitude is managed by tval_hold, tval_run, tval_acc and tval_dec registers (see table 14 on page 47 and section 9.1.10 on page 47 ). the voltage applied to the adcin pin is sampled at f s frequency and converted in an nadc bit digital signal. the analog-to-digital conv ersion result is available in the adc_out register. falling step 1 st fast decay: t fall = fall_step/4 falling step 1 st fast decay: t fall = fall_step/2 2 nd fast decay: t fall = fall_step/2 time reference current am15052v1
phase current control l6482 40/73 docid023768 rev 4 figure 21. current sensing and reference voltage generation load r sense to gate drivers to current control logic peak reference dac tval_x or adcin microstep microstepping dac to gate drivers to gate drivers to gate drivers sensex v ref am15047v1
docid023768 rev 4 41/73 l6482 serial interface 73 8 serial interface the integrated 8-bit serial peripheral interf ace (spi) is used for a synchronous serial communication between the host microprocessor (always master) and the l6482 (always slave). the spi uses chip select (cs ), serial clock (ck), serial da ta input (sdi) and serial data output (sdo) pins. when cs is high the device is unselected and the sdo line is inactive (high impedance). the communication starts when cs is forced low. the ck line is used for synchronization of data communication. all commands and data bytes are shifted into the device through the sdi input, most significant bit first. the sdi is samp led on the rising edges of the ck. all output data bytes are shifted out of the de vice through the sdo ou tput, most significant bit first. the sdo is latched on the falling edges of the ck. when a return value from the device is not available, an all zero byte is sent. after each byte transmission the cs input must be raised and be kept high for at least t discs in order to allow the device to decode the received command and put the return value into the shift register. all timing requirements are shown in figure 22 (see section 3 on page 11 for values). multiple devices can be connected in daisy chain configuration, as shown in figure 23 . figure 22. spi timings diagram am15053v1 ck sdi sdo cs msb lsb lsb n-1 n-2 msb hiz n-1 n-2 t setcs t ensdo t setsdi t holsdi t vsdo t holsdo t rck t fck t hck t lck t dissdo t holcs t discs msb
serial interface l6482 42/73 docid023768 rev 4 figure 23. daisy chain configuration
docid023768 rev 4 43/73 l6482 programming manual 73 9 programming manual 9.1 register and flag description table 11 shows the user registers available (a detailed description can be found in the respective paragraphs from section 9.1.1 on page 44 to section 9.1.21 on page 58 ): table 11. register map address [hex] register name register function len. [bit] reset [hex] reset value remarks (1) h01 abs_pos current position 22 000000 0 r, ws h02 el_pos electrical position 9 000 0 r, ws h03 mark mark position 22 000000 0 r, wr h04 speed current speed 20 000 00 0 step/tick (0 step/s) r h05 acc acceleration 12 08a 125.5e-12 step/tick 2 (2008 step/s 2 )r, ws h06 dec deceleration 12 08a 125.5e-12 step/tick 2 (2008 step/s 2 )r, ws h07 max_speed maximum speed 10 041 248e-6 step/tick (991.8 step/s) r, wr h08 min_speed minimum speed 12 000 0 step/tick (0 step/s) r, ws h15 fs_spd full-step speed 10 027 150.7e- 6 step/tick (602.7 step/s) r, wr h09 tval_hold holding reference voltage 729 328 mv r, wr h0a tval_run constant speed reference voltage 729 328 mv r, wr h0b tval_acc acceleration starting reference voltage 729 328 mv r, wr h0c tval_dec deceleration starting reference voltage 729 328 mv r, wr h0d reserved - 16 - - - h0e t_fast fast decay settings 8 19 1 s / 5 s r, wh h0f ton_min minimum on-time 8 29 20.5 s r, wh h10 toff_min minimum off-time 8 29 20.5 s r, wh h11 reserved - 8 - - - h12 adc_out adc output 5 xx (2) 0r h13 ocd_th ocd threshold 5 8 281.25 mv r, wr h14 reserved - 8 - - - h16 step_mode step mode 8 7 16 ? steps, sync mode disabled r, wh h17 alarm_en alarms enabled 8 ff all alarms enabled r, ws h18 gatecfg1 gate driver configuration 11 0 i gate = 4 ma, t cc = 125 ns, no boost r, wh
programming manual l6482 44/73 docid023768 rev 4 9.1.1 abs_pos the abs_pos register contains the current motor absolute po sition in agreement with the selected step mode; the stored value unit is e qual to the selected step mode (full, half, quarter, etc.). the value is in 2's complement format and it ranges from -2 21 to +2 21 -1. at power-on the register is init ialized to ?0? (home position). any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 9.1.21 on page 58 ). 9.1.2 el_pos the el_pos register contains the current elec trical position of the motor. the two msbits indicate the current step and the other bits in dicate the current microstep (expressed in step/16) within the step. when the el_pos register is written by the user, the new electrical position is instantly imposed. when the el_pos register is written, its value must be masked in order to match with the step mode selected in the step_mo de register in order to avoid a wrong microstep value generation ( section 9.1.17 on page 52 ); otherwise the resulting microstep sequence is incorrect. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 9.1.21 ). h19 gatecfg2 gate driver configuration 80 t blank = 125 ns, t dt = 125 ns r, wh h1a config ic configuration 16 2c88 internal 16 mhz oscillator (oscout at 2 mhz), sw event causes hardstop, motor supply voltage compensation disabled, overcurrent shutdown, v cc = 7.5 v, uvlo threshold low, t sw = 44 s r, wh h1b status status 16 xxxx (2) high impedance state, motor stopped, reverse direction, all fault flags released uvlo/reset flag set r 1. r: readable, wh: writable, only when outputs are in high impedance, ws: writable only when motor is stopped, wr: always writable. 2. according to startup conditions. table 11. register map (continued) address [hex] register name register function len. [bit] reset [hex] reset value remarks (1) table 12. el_pos register bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 step microstep 0 0 0
docid023768 rev 4 45/73 l6482 programming manual 73 9.1.3 mark the mark register contains an absolute position called mark, according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). it is in 2's complement format and it ranges from -2 21 to +2 21 -1. 9.1.4 speed the speed register contains the current moto r speed, expressed in step/tick (format unsigned fixed point 0.28). in order to convert the speed value in step/s, the fo llowing formula can be used: equation 1 where speed is the integer number stored in the register and tick is 250 ns. the available range is from 0 to 15625 st ep/s with a resolution of 0.015 step/s. note: the range effectively av ailable to the user is limit ed by the max_speed parameter. any attempt to write the register causes the command to be ignored and the cmd_error flag to rise ( section 9.1.21 on page 58 ). 9.1.5 acc the acc register contains the speed prof ile acceleration expressed in step/tick 2 (format unsigned fixed point 0.40). in order to convert the acc value in step/s 2 , the following formula can be used: equation 2 where acc is the integer number stored in the register and tick is 250 ns. the available range is from 14.55 to 59590 step/s 2 with a resolution of 14.55 step/s 2 . the 0xfff value of the register is re served and it should never be used. any attempt to write to the re gister when the motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 9.1.21 ). 9.1.6 dec the dec register contains the speed prof ile deceleration expr essed in step/tick 2 (format unsigned fixed point 0.40). step/s ?? speed 2 28 ? ? tick ------------------------------------- = step/s 2 ?? acc 2 40 ? ? tick 2 ---------------------------- - =
programming manual l6482 46/73 docid023768 rev 4 in order to convert the dec value in step/s 2 , the following formula can be used: equation 3 where dec is the integer number stored in the register and tick is 250 ns. the available range is from 14.55 to 59590 step/s2 with a resolution of 14.55 step/s2. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 9.1.21 on page 58 ). 9.1.7 max_speed the max_speed register contains the spee d profile maximum sp eed expres sed in step/tick (format unsigned fixed point 0.18). in order to convert it in step/s, the following formula can be used: equation 4 where max_speed is the integer number stored in the register and tick is 250 ns. the available range is from 15.25 to 15610 step/s with a resolution of 15.25 step/s. 9.1.8 min_speed the min_speed register contains the following parameters: the min_speed parameter contai ns the speed profile mini mum speed. its value is expressed in step/tick and to convert it in step/s the following formula can be used: equation 5 where min_speed is the integer number stored in the register and tick is the ramp 250 ns. the available range is from 0 to 976.3 step/s with a resolution of 0.238 step/s. any attempt to write the register when the mo tor is running causes the cmd_error flag to rise. step/s 2 ?? dec 2 40 ? ? tick 2 ---------------------------- - = step/s ?? max_speed 2 18 ? ? tick ----------------------------------------------------- = table 13. min_speed register bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 min_speed step/s ?? min_speed 2 24 ? ? tick --------------------------------------------------- =
docid023768 rev 4 47/73 l6482 programming manual 73 9.1.9 fs_spd the fs_spd register contains the following parameters: the fs_spd threshold speed value over which the step mode is autom atically switched to full-step two-phase on. its value is expressed in step/tick (format unsigned fixed point 0.18) and to convert it in step/s the following formula can be used: equation 6 if fs_spd value is set to hff (max.) the system always works in microstepping mode (speed must go over the threshold to switch to full-step mode). setting fs_spd to zero does not have the same effect as setting the step mode to full-step two-phase on: the zero fs_spd value is equivalent to a speed threshold of about 7.63 step/s. the available range is from 7.63 to 15625 step/s with a resolution of 15.25 step/s. the boost_mode bit sets the amplitude of the voltage squarewave during the full-step operation (see section : automatic full-step and boost modes on page 21 ). 9.1.10 tval_hold, tval_run, tval_acc and tval_dec the tval_hold register contains the referenc e voltage that is assigned to the torque regulation dac when the motor is stopped. the tval_run register contains the referenc e voltage that is assigned to the torque regulation dac when the motor is running at constant speed. the tval_acc register contains the reference voltage that is assigned to the torque regulation dac during acceleration. the tval_dec register contains the reference voltage that is assigned to the torque regulation dac dur ing deceleration. the available range is from 7.8 mv to 1 v with a resolution of 7.8 mv, as shown in table 15. table 14. fs_spd register bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 boost_mode fs_spd step/s ?? fs_spd 0.5 + ?? 2 18 ? ? tick ---------------------------------------------------------- - =
programming manual l6482 48/73 docid023768 rev 4 9.1.11 t_fast the t_fast register contains the maximum fast decay time (toff_fast) and the maximum fall step time (fall_step) us ed by the current control system ( section 7.2 on page 36 and section 7.3 on page 38 for details): the available range for both parameters is from 2 s to 32 s. any attempt to write to the re gister when the motor is running causes the command to be ignored and cmd_error to rise ( section 9.1.21 on page 58 ). 9.1.12 ton_min this parameter is used by the current control system when current mode operation is selected. the ton_min register contains the minimum on-time value used by the current control system (see section 7.2 ). the available range for both parame ters is from 0.5 s to 64 s. table 15. torque regulation by tval_hol d, tval_acc, tval_dec and tval_run registers tval_x [6?0] peak reference voltage 0000000 7.8 mv 0000001 15.6 mv ? ? ? ? ? ? ? ? 1111110 992.2 mv 1111111 1 v table 16. fs_spd register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 toff_fast fast_step table 17. maximum fast decay times toff_fast [3?0] fast_step [3?0] fast decay time 0 0 0 0 2 s 0 0 0 1 4 s ? ? ? ? ? 1 1 1 0 28 s 1 1 1 1 32 s
docid023768 rev 4 49/73 l6482 programming manual 73 any attempt to write to the re gister when the motor is running causes the command to be ignored and the cmd_error to rise (see section 9.1.21 on page 58 ). 9.1.13 toff_min this parameter is used by the current control system when current mode operation is selected. the toff_min register contains the minimum of f-time value used by the current control system (see section 7.1 on page 35 for details). the available range for both parameters is from 0.5 s to 64 s. any attempt to write to the re gister when the motor is running causes the command to be ignored and cmd_error to rise (see section 9.1.21 ). table 18. minimum on-time ton min [6?0] time 0 0 0 0 0 0 0 0.5 s 0 0 0 0 0 0 1 1 s ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 63.5 s 1 1 1 1 1 1 1 64 s table 19. minimum off-time toff min [6?0] time 0 0 0 0 0 0 0 0.5 s 0 0 0 0 0 0 1 1 s ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 63.5 s 1 1 1 1 1 1 1 64 s
programming manual l6482 50/73 docid023768 rev 4 9.1.14 adc_out the adc_out register contains the result of the analog-to-digital conversion of the adcin pin voltage. any attempt to write to the register causes the command to be ignored and the cmd_error flag to rise (see section 9.1.21 on page 58 ). 9.1.15 ocd_th the ocd_th register contains the overcurrent threshold value (see section 6.9 on page 27 for details). the available range is from 31.25 mv to 1 v, steps of 31.25 mv, as shown in table 21 . 9.1.16 step_mode the step_mode register has the following structure: table 20. adc_out value and torque regulation feature vadcin/ vreg adc_out [4?0] reference voltage 0 0 0 0 0 0 31.25 mv 1/32 0 0 0 0 1 62.5 mv ? ? ? ? ? ? ? 30/32 1 1 1 1 0 968.8 mv 31/32 1 1 1 1 1 1 v table 21. overcurrent detection threshold ocd_th [4?0] overcurrent detection threshold 0 0 0 0 0 31.25 mv 0 0 0 0 1 62.5 mv ? ? ? ? ? ? 1 1 1 1 0 968.8 mv 1 1 1 1 1 1 v table 22. step_mode register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sync_en sync_sel 1 (1) 1. when the register is written this bit must be set to 1. step_sel
docid023768 rev 4 51/73 l6482 programming manual 73 the step_sel parameter selects one of five possible stepping modes: every time the step mode is changed, the electr ical position (i.e. the point of microstepping sine wave that is generated) is reset to the first microstep. warning: every time step_sel is ch anged, the value in the abs_pos register loses meaning and should be reset. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_erro r flag to rise (see section 9.1.21 on page 58 ). when the sync_en bit is set low, the busy /sync output is forced low during the command execution, otherwise, when the sync_en bit is set high, the busy /sync output provides a clock signal according to the sync_sel parameter. table 23. step mode selection step_sel[2?0] step mode 0 0 0 full-step 0 0 1 half-step 0 1 0 1/4 microstep 0 1 1 1/8 microstep 1 x x 1/16 microstep table 24. sync output frequency step_sel (f fs is the full-s tep frequency) 000 001 010 011 100 101 110 111 sync_sel 000 f fs /2 f fs /2 f fs /2 f fs /2 f fs /2 f fs /2 f fs /2 f fs /2 001 na f fs f fs f fs f fs f fs f fs f fs 010 na na 2 f fs 2 f fs 2 f fs 2 f fs 2 f fs 2 f fs 011 na na na 4 f fs 4 f fs 4 f fs 4 f fs 4 f fs 100 na na na na 8 f fs 8 f fs 8 f fs 8 f fs 101 na na na na na na na na 110 na na na na na na na na 111 na na na na na na na na
programming manual l6482 52/73 docid023768 rev 4 the synchronization signal is obtained starting from the electrical position information (el_pos register), according to table 25 : 9.1.17 alarm_en the alarm_en register allows the selection of which alarm signals are used to generate the flag output. if the respective bit of the al arm_en register is set high, the alarm condition forces the flag pin output down. 9.1.18 gatecfg1 the gatecfg1 register has the following structure: table 25. sync signal source sync_sel[2?0] source 0 0 0 el_pos[7] 0 0 1 el_pos[6] 0 1 0 el_pos[5] 0 1 1 el_pos[4] 1 0 0 el_pos[3] 1 0 1 unused (1) 1. when this value is selected, the busy output is forced low. 1 1 0 unused (1) 1 1 1 unused (1) table 26. alarm_en register alarm_en bit alarm condition 0 (lsb) overcurrent 1 thermal shutdown 2 thermal warning 3uvlo 4 adc uvlo 5 unused 6 switch turn-on event 7 (msb) command error table 27. gatecfg1 register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 wd_en tboost bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 igate tcc
docid023768 rev 4 53/73 l6482 programming manual 73 the igate parameter selects the sink/source current used by gate driving circuitry to charge/discharge the respective gate during commutations. seven possible values ranging from 4 ma to 96 ma are available, as shown in table 28 . the tcc parameter defines the duration of constant current phase during gate turn-on and turn-off sequences ( section 6.15 on page 31 ). the tboost parameter defines the duration of the overboost phase during gate turn-off ( section 6.15 ). table 28. igate parameter igate [2?0} gate current [ma} 000 4 001 4 010 8 011 16 100 24 101 32 110 64 111 96 table 29. tcc parameter tcc [4?0] constant current time [ns] 00000 125 00001 250 ????? ? 11100 3625 11101 3750 11110 3750 11111 3750
programming manual l6482 54/73 docid023768 rev 4 the wd_en bit enables the clock source monitoring ( section 6.8.2 on page 26 ). 9.1.19 gatecfg2 the gatecfg2 register has the following structure: the tdt parameter defines the deadtime duration between the gate turn-off and the opposite gate turn-on sequences ( section 6.16 on page 32 ). the tblank parameter defines the duration of the blanking of the current sensing comparators (stall detection and overcurrent) after each commutation ( section 6.16 ). table 30. tboost parameter tboost turn-off boost time [ns] [2?0] 000 0 00162.5 (1) / 83.3 (2) / 125 (3) 1. clock frequency equal to 16 mhz or 32 mhz. 2. clock frequency equal to 24 mhz. 3. clock frequency equal to 8 mhz. 010125 011250 100375 101500 110750 1 1 1 1000 table 31. gatecfg2 register (voltage mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tblank tdt table 32. tdt parameter tdt [4?0] deadtime [ns] 00000 125 00001 250 ????? ? 11110 3875 11111 4000
docid023768 rev 4 55/73 l6482 programming manual 73 9.1.20 config the config register has the following structure: table 33. tblank parameters tblank [2?0] blanking time [ns] 000 125 001 250 ??? ? 110 875 1 1 1 1000 table 34. config register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 pred_en tsw vccval uvloval bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oc_sd reserved en_tqreg sw_mode ext_clk osc_sel
programming manual l6482 56/73 docid023768 rev 4 the osc_sel and ext_clk bits set the system clock source: the sw_mode bit sets the external switch to act as hardstop interrupt or not: table 35. oscilla tor management ext_clk osc_sel [2?0] clock source oscin oscout 0000 internal oscillator: 16 mhz unused unused 0001 0010 0011 1 0 0 0 internal oscillator: 16 mhz unused supplies a 2-mhz clock 1 0 0 1 internal oscillator: 16 mhz unused supplies a 4-mhz clock 1 0 1 0 internal oscillator: 16 mhz unused supplies an 8-mhz clock 1 0 1 1 internal oscillator: 16 mhz unused supplies a 16-mhz clock 0 1 0 0 external crystal or resonator: 8 mhz crystal/resonator driving crystal/resonator driving 0 1 0 1 external crystal or resonator: 16 mhz crystal/resonator driving crystal/resonator driving 0 1 1 0 external crystal or resonator: 24 mhz crystal/resonator driving crystal/resonator driving 0 1 1 1 external crystal or resonator: 32 mhz crystal/resonator driving crystal/resonator driving 1100 ext. clock source: 8 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1101 ext. clock source: 16 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1110 ext. clock source: 24 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1111 ext. clock source: 32 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal table 36. external switch hardstop interrupt mode sw_mode switch mode 0 hardstop interrupt 1 user disposal
docid023768 rev 4 57/73 l6482 programming manual 73 the oc_sd bit sets if an overcurrent event ca uses or not the bridges to turn off; the ocd flag in the status register is forced low anyway: the vccval bit sets the internal v cc regulator output voltage. table 38. programmable v cc regulator output voltage the uvloval bit sets the uvlo protection thresholds. table 39. programmable uvlo thresholds the en_tqreg bit sets if the torque regulation is performed through adcin voltage (external) or the tval_hold, tval_acc, tval_dec and tval_run registers (internal). the tsw parameter is used by the current control system and it sets the target switching period. table 37. overcurrent event oc_sd overcurrent event 1 bridges shutdown 0 bridges do not shutdown vccval v cc voltage 0 7.5 v 115 v uvloval v ccthon v ccthoff ? v bootthon ? v bootthoff 0 6.9 v 6.3 v 6 v 5.5 v 1 10.4 v 10 v 9.2 v 8.8 v table 40. external torque regulation enable en_tqreg external torque regulation 0 disabled 1 enabled table 41. switching period tsw [4?0] switching period 0 0 0 0 0 4 s (250 khz) 0 0 0 0 1 4 s (250 khz) 0 0 0 1 0 8 s (125 khz) ? ? ? ? ? ? 1 1 1 1 1 124 s (8 khz)
programming manual l6482 58/73 docid023768 rev 4 any attempt to write the config register wh en the motor is running causes the command to be ignored and the cmd_error flag to rise (see section 9.1.21 on page 58 ). the pred_en bit sets if the predictive cu rrent control method is enabled or not. . any attempt to write the config register wh en the motor is running causes the command to be ignored and the cmd_error flag to rise ( section 9.1.20 on page 55 ). 9.1.21 status the status register has the following structure: when the hiz flag is high it indicates that the bridges are in high impedance state. any motion command causes the device to exit fr om high z state (hardstop and softstop included), unless error flags forcing a high z state are active. the uvlo flag is active low and is set by an undervoltage lockout or reset events (power-up included). the uvlo_adc flag is active low and indicates an adc undervoltage event. the ocd flag is active low and indi cates an overcurrent detection event. the cmd_error flag is active high and indica tes that the command received by spi can't be performed or does not exist at all. the sw_f reports the sw input status (low for open and high for closed). the sw_evn flag is active high and indicates a switch tu rn-on event (sw input falling edge). table 42. motor supply voltage compensation enable pred_en predictive current control 0 disabled 1 enabled table 43. status register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 unused unused ocd th_status uvlo_adc uvlo stck_mod bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmd_error mot_status dir sw_evn sw_f busy hiz
docid023768 rev 4 59/73 l6482 programming manual 73 th_status bits indicate the current device thermal status ( section 6.12 on page 29 ): uvlo, uvlo_adc, ocd, cmd_error, sw_e vn and th_status bits are latched: when the respective conditions make them active (low or high) they remain in that state until a getstatus command is sent to the ic. the busy bit reflects the busy pin status. th e busy flag is low when a constant speed, positioning or motion command is under exec ution and is released (high) after the command has been completed. the stck_mod bit is an active high flag indica ting that the device is working in step-clock mode. in this case the step-clock signal sh ould be provided through the stck input pin. the dir bit indicates the current motor direction: mot_status indicates the current motor status: any attempt to write to the register causes the command to be ignored and the cmd_error to rise. table 44. status register th_status bits th_status status 0 0 normal 01warning 1 0 bridge shutdown 1 1 device shutdown table 45. status register dir bit dir motor direction 1forward 0reverse table 46. status register mot_status bits mot_status motor status 0 0 stopped 0 1 acceleration 1 0 deceleration 1 1 constant speed
programming manual l6482 60/73 docid023768 rev 4 9.2 application commands the command summary is given in table 47 . table 47. application commands command mnemonic command binary code action [7?5] [4] [3] [2?1] [0] nop 000 0 0 00 0 nothing setparam (param, value) 000 [param] writes value in param register getparam (param) 001 [param] returns the stored value in param register run (dir, spd) 010 1 0 00 dir sets the target speed and the motor direction stepclock (dir) 010 1 1 00 dir puts the device in step-clock mode and imposes dir direction move (dir,n_step) 010 0 0 00 dir makes n_step (micro)steps in dir direction (not performable when motor is running) goto (abs_pos) 011 0 0 00 0 brings motor in abs_pos position (minimum path) goto_dir (dir, abs_pos) 011 0 1 00 dir brings motor in abs_pos position forcing dir direction gountil (act, dir, spd) 100 0 act 01 dir performs a motion in dir direction with speed spd until sw is closed, the act action is executed then a softstop takes place rele a sesw (act, dir) 100 1 act 01 dir performs a motion in dir direction at minimum speed until the sw is released (open), the act action is executed then a hardstop takes place gohome 011 1 0 00 0 brings the motor in home position gomark 011 1 1 00 0 brings the motor in mark position resetpos 110 1 1 00 0 resets the abs_pos register (sets home position) resetdevice 110 0 0 00 0 device is reset to power-up conditions softstop 101 1 0 00 0 stops motor with a deceleration phase hardstop 101 1 1 00 0 stops motor immediately softhiz 101 0 0 00 0 puts the bridges in high impedance status after a deceleration phase hardhiz 101 0 1 00 0 puts the bridges in high impedance status immediately getstatus 110 1 0 00 0 returns the status register value reserved 111 0 1 01 1 reserved command reserved 111 1 1 00 0 reserved command
docid023768 rev 4 61/73 l6482 programming manual 73 9.2.1 command management the host microcontroller can control motor motion and configure the l6482 device through a complete set of commands. all commands are composed by a single byte. after the command byte, some bytes of arguments should be needed (see figure 24 ). argument length can vary from 1 to 3 bytes. figure 24. command with 3-byte argument by default, the device returns an all zero response for any received byte, the only exceptions are getparam and getstatus commands. when one of these commands is received, the following response bytes represent the related register value (see figure 25 ). response length can va ry from 1 to 3 bytes. figure 25. command with 3-byte response during response transmission, new commands can be sent. if a command requiring a response is sent before the previous response is completed, the response transmission is aborted and the new response is loaded into the output communication buffer (see figure 26 ). figure 26. command response aborted when a byte that does not correspond to a comma nd is sent to the ic it is ignored and the cmd_error flag in the status register is raised (see section 9.1.21 on page 58 ). sdi sdo command byte argument byte 2 (msb) argument byte 0 (lsb) argument byte 1 0x00 0x00 0x00 0x00 (from host) (to host) am15055v1 sdi sdo command byte response byte 2 (msb) response byte 0 (lsb) response byte 1 0x00 nop nop nop (from host) (to host) am15056v1 sdi sdo command 1 (3 byte resp expected) command 3 (2 byte resp expected) response byte 2 (msb) response byte 1 (msb) response byte 1 0x00 command 2 (no resp. expected) response byte 0 (lsb) (from host) (to host) command 4 (no resp. expected) command 5 (no resp. expected) command 1 response is aborted am15057v1
programming manual l6482 62/73 docid023768 rev 4 9.2.2 nop nothing is performed. 9.2.3 setparam (param, value) the setparam command sets the param register value equal to value; param is the respective register address listed in table 11 on page 43 . the command should be followed by the new register value (most significant byte first). the number of bytes composing the value argu ment depends on the length of the target register (see table 11 ). some registers cannot be written (see table 11 ); any attempt to write one of those registers causes the command to be ignored and the cmd_error flag to rise at the end of the command byte, as if an unknown command code were sent (see section 9.1.21 on page 58 ). some registers can only be writte n in particular conditions (see table 11 ); any attempt to write one of those registers when the conditions are not satisfied causes the command to be ignored and the cmd_error flag to rise at the end of the last argument byte (see section 9.1.21 ). any attempt to set an inexistent register (wrong address value) causes the command to be ignored and the cmd_error flag to rise at the end of the command byte as if an unknown command code were sent. 9.2.4 getparam (param) table 48. nop command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000000 from host table 49. setparam command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000 param from host value byte 2 (if needed) value byte 1 (if needed) value byte 0 table 50. getparam command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 param from host ans byte 2 (if needed) to host ans byte 1 (if needed) to host ans byte 0 to host
docid023768 rev 4 63/73 l6482 programming manual 73 this command reads the current param register value; param is the respective register address listed in table 11 on page 43 . the command response is the current value of the register (most significant byte first). the number of bytes composing the command resp onse depends on the length of the target register (see table 11 ). the returned value is the register one at the moment of getparam command decoding. if register values change after this moment, the response is not updated accordingly. all registers can be read anytime. any attempt to read an inexistent register (wrong address value) causes the command to be ignored and the cmd_error flag to rise at the end of the command byte as if an unknown command code were sent. 9.2.5 run (dir, spd) the run command produces a motion at spd s peed; the direction is selected by the dir bit: '1' forward or '0' reverse. the spd value is expressed in step/tick (format unsigned fixed point 0.28) that is the same format as the speed register ( section 9.1.4 on page 45 ). note: the spd value should be lower th an max_speed and greater than min_speed, otherwise the run co mmand is executed at max_speed or min_spe ed respectively. this command keeps the busy flag low until the target speed is reached. this command can be given anytim e and is immediately executed. 9.2.6 stepclock (dir) the stepclock command switches the device in step-clock mode ( section 6.7.5 on page 25 ) and imposes the forward (dir = '1') or reverse (dir = '0') direction. when the device is in step-clock mode, the sck_ mod flag in the status register is raised and the motor is always considered stopped ( section 6.7.5 and 9.1.21 on page 58 ). the device exits step-clock mode when a cons tant speed, absolute positioning or motion command is sent through spi. motion directio n is imposed by the respective stepclock command argument and can by changed by a new stepclock command without exiting step-clock mode. table 51. run command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 0101000dir from host xxxx spd (byte 2) from host spd (byte 1) from host spd (byte 0) from host table 52. stepclock command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0101100dirfrom host
programming manual l6482 64/73 docid023768 rev 4 events that cause bridges to be forced into high impedance state (overtemperature, overcurrent, etc.) do not cause the device to leave step-clock mode. the stepclock command does not force the busy flag low. this command can only be given when the motor is stopped. if a motion is in progress, the mo tor should be stopped and it is then possible to send a stepclock command. any attempt to perform a stepclock command when the motor is running causes the command to be ignored and the cmd_error flag to rise ( section 9.1.21 on page 58 ). 9.2.7 move (dir, n_step) the move command produces a motion of n_step microsteps; the direction is selected by the dir bit ('1' forward or '0' reverse). the n_step value is always in agreement wi th the selected step mode; the parameter value unit is equal to th e selected step mode (full, half, quarter, etc.). this command keeps the busy flag low until the target number of steps is performed. this command can only be performed when the motor is stopped. if a motion is in progress the motor must be stopped and it is then possible to perform a move command. any attempt to perform a move command when the motor is running causes the command to be ignored and the cmd_error flag to rise ( section 9.1.21 ). 9.2.8 goto (abs_pos) the goto command prod uces a motion to the abs_pos ab solute position through the shortest path. the abs_pos valu e is always in agreement with the selected step mode; the parameter value unit is equal to the selected step mode (full, half, quarter, etc.). the goto command keeps the busy flag low until the target position is reached. this command can be given only when the previous motion command has been completed (busy flag released). table 53. move command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0100000dirfrom host x x n_step (byte 2) from host n_step (byte 1) from host n_step (byte 0) from host table 54. goto command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 1 00000 from host x x abs_pos (byte 2) from host abs_pos (byte 1) from host abs_pos (byte 0) from host
docid023768 rev 4 65/73 l6482 programming manual 73 any attempt to perform a goto command when a previous command is under execution (busy low) causes the command to be ignored and the cmd_error flag to rise ( section 9.1.21 on page 58 ). 9.2.9 goto_dir (dir, abs_pos) the goto_dir command produces a motion to the abs_pos absolute position imposing a forward (dir = '1') or a re verse (dir = '0') rotation. the abs_pos value is always in agreement with the selected st ep mode; the paramete r value unit is equa l to the selected step mode (full, half, quarter, etc.). the goto_dir command keeps the busy flag low until the target speed is reached. this command can be given only when the previous motion command has been completed (busy flag released). any attempt to perform a goto_dir command when a previous command is under execution (busy low) causes the command to be ignored and the cmd_error flag to rise ( section 9.1.21 ). 9.2.10 gountil (act, dir, spd) the gountil command produces a motion at spd speed imposing a forward (dir = '1') or a reverse (dir = '0') direction. when an external switch turn-on event occurs ( section 6.14 on page 30 ), the abs_pos register is reset (if act = '0') or the abs_pos register value is copied into the mark register (if act = '1'); the system then performs a softstop command. the spd value is expressed in step/tick (format unsigned fixed point 0.28) that is the same format as the speed register ( section 9.1.4 on page 45 ). the spd value should be lower than max_speed and greater than min_speed, otherwise the target speed is imposed at max_speed or min_speed respectively. if the sw_mode bit of the config register is set low, the external switch turn-on event causes a hardstop interrupt instead of the softstop one ( section 6.14 on page 30 and table 55. goto_dir command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0110100dirfrom host x x abs_pos (byte 2) from host abs_pos (byte 1) from host abs_pos (byte 0) from host table 56. gountil command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1000act01dir from host x x x x spd (byte 2) from host spd (byte 1) from host spd (byte 0) from host
programming manual l6482 66/73 docid023768 rev 4 section 9.1.20 on page 55 ). this command keeps the busy flag low until the switch turn-o n event occurs and the motor is stopped. this command can be give n anytime and is i mmediately executed. 9.2.11 releasesw (act, dir) the releasesw command produces a motion at minimum speed imposing a forward (dir = '1') or reverse (dir = '0') rotation. when sw is released (opened) the abs_pos register is reset (act = '0') or the abs_pos register value is copied into the mark register (act = '1'); the system then performs a hardstop command. note that, resetting the abs_pos register is equivalent to setting the home position. if the minimum speed value is less than 5 step /s or low speed optimi zation is enabled, the motion is performed at 5 step/s. the releasesw command keeps the busy flag lo w until the switch i nput is released and the motor is stopped. 9.2.12 gohome the gohome command produces a motion to the home position (zero position) via the shortest path. note that, this command is equivalent to th e ?goto(0?0)? command. if a motor direction is mandatory, the goto_dir command must be used ( section 9.2.9 ). the gohome command keeps the busy flag low until the home position is reached. this command can be given only when the previous motion command has been completed. any attempt to perform a gohome command when a previous command is under execution (busy low) causes the command to be ignored and the cmd_error to rise ( section 9.1.21 on page 58 ). 9.2.13 gomark table 57. releasesw command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 0 1 act 0 1 dir from host table 58. gohome command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 01110000 from host table 59. gomark command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01111000from host
docid023768 rev 4 67/73 l6482 programming manual 73 the gomark command produces a motion to th e mark position performing the minimum path. note that, this command is equivalent to th e ?goto (mark)? command. if a motor direction is mandatory, the goto_dir command must be used. the gomark command keeps the busy flag low until the mark position is reached. this command can be given only when the previous motion command has been completed (busy flag released). any attempt to perform a gomark command when a previous command is under execution (busy low) causes the command to be ignored and the cmd_error flag to rise ( section 9.1.21 on page 58 ). 9.2.14 resetpos the resetpos command resets the abs_pos register to zero. the zero position is also defined as the home position ( section 6.5 on page 22 ). 9.2.15 resetdevice the resetdevice command resets the device to power-up conditions ( section 6.1 on page 19 ). the command can be performed only when the device is in high impedance state. note: at power-up the power bridges are disabled. 9.2.16 softstop the softstop command causes an immediate dece leration to zero speed and a consequent motor stop; the deceleration value used is the one stored in the dec register ( section 9.1.6 on page 45 ). when the motor is in high impedance state, a softstop command forces the bridges to exit from high impedance state; no motion is performed. this command can be given anytime and is immediately executed. this command keeps the busy flag low until the motor is stopped. table 60. resetpos command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 11011000 from host table 61. resetdevice command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 11000000 from host table 62. softstop command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 10110000 from host
programming manual l6482 68/73 docid023768 rev 4 9.2.17 hardstop the hardstop command causes an immediate motor stop with infinite deceleration. when the motor is in high impedance state, a hardstop command forces the bridges to exit high impedance state; no motion is performed. this command can be given anytime and is immediately executed. this command keeps the busy flag low until the motor is stopped. 9.2.18 softhiz the softhiz command disables the power bridges (high impedance state) after a deceleration to zero; the deceleration value used is the one stored in the dec register ( section 9.1.6 on page 45 ). when bridges are disabled, the hiz flag is raised. when the motor is stopped, a softhiz command forces the bridges to enter high impedance state. this command can be given anytime and is immediately executed. this command keeps the busy flag low until the motor is stopped. 9.2.19 hardhiz the hardhiz command immediately disables th e power bridges (high impedance state) and raises the hiz flag. when the motor is stopped, a hardhiz command forces the bridges to enter high impedance state. this command can be given anytim e and is immediately executed. this command keeps the busy flag low until the motor is stopped. table 63. hardstop command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 10111000 from host table 64. softhiz command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10100000 from host table 65. hardhiz command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10101000 from host
docid023768 rev 4 69/73 l6482 programming manual 73 9.2.20 getstatus the getstatus command returns the status register value. the getstatus command resets the status re gister warning flags. the command forces the system to exit from any error state. the getstatus co mmand does not reset the hiz flag. table 66. getstatus command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 11010000 from host status msbyte to host status lsbyte to host
package information l6482 70/73 docid023768 rev 4 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com. ecopack is an st trademark. figure 27. htssop38 package outline table 67. htssop38 package mechanical data symbol dimensions (mm) min. typ. max. a-1.1 a1 0.05 - 0.15 a2 0.85 0.9 0.95 b 0.17 - 0.27 c 0.09 - 0.20 d 9.60 9.70 9.80 e1 4.30 4.40 4.50 e - 0.50 - e - 6.40 - l 0.50 0.60 0.70 p 6.40 6.50 6.60 p1 3.10 3.20 3.30 ? 0 - 8 f ( ( $ $ $ e ' 3 3 pp ? / ? h
docid023768 rev 4 71/73 l6482 package information 73 figure 28. htssop38 footprint
revision history l6482 72/73 docid023768 rev 4 11 revision history table 68. document revision history date revision changes 08-oct-2012 1 initial release. 19-dec-2012 2 changed the title. inserted footnote in ta ble 2 and ta ble 4 removed tj parameter in table 3 . updated section 9.1.10 and section 9.1.15 . updated table 17 . minor text changes. 13-dec-2013 3 updated section 6.3 (replaced ?integrated mosf ets? by ?gate drivers?). updated section 6.9 to section 6.13 (replaced ?gates? by ?mosfets?). added cross-references to section 9 . updated section 9.1.19 (replaced ?tcc paramete r? by ?tdt parameter?). updated section 9.2.15 (added ?the command can be performed only when the device is in high impedance state.?). updated section 10 (updated titles, reversed order of figure 27 and table 67 ). minor modifications throughout document. 19-may-2014 4 updated table 2 on page 9 [added (v boot - v s ) to ? v boot ]. updated table 5 on page 11 (updated i vregqu and i vregq symbols, values of t high,stck , t low,stck , and t high symbols). updated table 7 on page 18 (replaced std25nf10 by std25n10f7). updated section 6.1 on page 19 (removed v cc and v boot , added flag output...). updated section 6.4 on page 20 (replaced ?the first microstep? by ?zero?). removed section ?infinite accelerati on/deceleration mode? from page 23. replaced notperf_cmd and wrong_cmd flag by cmd_error flag throughout document. updated section 9.1.5 on page 45 (replaced sentence: ?when the acc value is set to 0xfff, the device works in infinite acceleration mode.? by ?the 0xfff value of the register is reserved and it should never be used.?). updated section 9.1.6 on page 45 (removed sentence: ?when the device is working in infinite acceleration mode this value is ignored.?). updated section 9.1.20 on page 55 (replaced pred_e and en_pred by pred_en ). updated table 43 on page 58 (replaced th_sd by th_status). updated title of table 46 on page 59 (replaced mot_state by mot_status). updated cross-references throughout document.
docid023768 rev 4 73/73 l6482 73 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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